1. Field of the Invention
The present invention is related to a latch system applied to a plurality of banks of a memory circuit, and particularly to a latch system that includes a front latch circuit and a plurality of rear latch circuits, where the front latch circuit and the plurality of rear latch circuits are not turned on simultaneously.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a latch system 100 applied to a plurality of banks of a memory circuit according to the prior art. The latch system 100 has a plurality of latch circuits L0 to Ln−1, where each latch circuit corresponds to a bank. For example, a latch circuit L0 corresponds to a bank B0, a latch circuit L1 corresponds to a bank B1, and so on. Each latch circuit has a first input terminal for receiving a datum, a second input terminal for receiving a corresponding latch enabling signal, and an output terminal for outputting a latch datum to a corresponding bank. For example, after the latch circuit L0 receives a datum D and a latch enabling signal LE0, the latch circuit L0 generates and outputs a latch datum LD0 to the bank B0 according to the datum D and the latch enabling signal LE0. As shown in FIG. 1, a transmission gate T00 and a transmission gate T01 of the latch circuit L0 are not turned on and off simultaneously. That is to say, when the transmission gate T00 is turned on, the transmission gate T01 is turned off; and when the transmission gate T00 is turned off, the transmission gate T01 is turned on.
Please refer to FIG. 2. FIG. 2 is a timing diagram illustrating an operation timing of the latch system 100. As shown in FIG. 1 and FIG. 2, at a first interval T1, a transmission gate T00 is turned on and a transmission gate T01 is turned off. Because the transmission gate T00 is turned on, an intermediate signal IS is equal to the datum D. The transmission gate T01 is turned off, so a signal LD0 of an output terminal of the latch circuit L0 is unknown. At a second interval T2, the latch circuit L0 receives a latch enabling signal LE0, so the transmission gate T00 is turned off and the transmission gate T01 is turned on. Because the transmission gate T00 is turned off and the transmission gate T01 is turned on, the intermediate signal IS maintains a value of the intermediate signal IS at the second interval T1, and the signal LD0 of the output terminal of the latch circuit L0 is equal to the intermediate signal IS. At a third interval T3, when the latch enabling signal LE0 changes from a logical-high voltage “1” to a logical-low voltage “0”, the transmission gate T00 is turned on and the transmission gate T01 is turned off. Because the transmission gate T00 is turned on, the intermediate signal IS is equal to the datum D. The transmission gate T01 is turned off, so the signal LD0 of the output terminal of the latch circuit L0 maintains a value of the intermediate signal IS at the second interval T2. Further, subsequent operational principles of other latch circuits of the latch system 100 are the same as those of the latch circuit L0, so further description thereof is omitted for simplicity.
Please refer to FIG. 3. FIG. 3 is a diagram illustrating unpredictability of the signal LD0 of the output terminal of the latch circuit L0 when a negative edge of the latch enabling signal LE0 is not sharp enough. As shown in FIG. 3, at the third interval T3, because the latch enabling signal LE0 changes from the logical-high voltage “1” to the logical-low voltage “0” too slowly, the transmission gate T00 and the transmission gate T01 are turned on simultaneously, resulting in the signal LD0 of the output terminal of the latch circuit L0 being equal to the intermediate signal IS at the third interval T3, instead of maintaining the value of the intermediate signal IS at the second interval T2.
To sum up, the latch system 100 utilizes the latch enabling signal LE0 to control the transmission gate T00 and the transmission gate T01 simultaneously, so the signal LD0 of the output terminal of the latch circuit L0 may be unpredictable. Thus, the latch system 100 is not a good choice for a user.